hwtGraph.elk.fromHwt package

Submodules

hwtGraph.elk.fromHwt.convertor module

hwtGraph.elk.fromHwt.convertor.UnitToLNode(u: Unit, node: LNode | None = None, toL: dict | None = None, optimizations=[]) LNode

Build LNode instance (a graph) from hwt.synthesizer.unit.Unit instance (a RTL graph)

Attention:

unit has to be synthesized

hwtGraph.elk.fromHwt.defauts module

hwtGraph.elk.fromHwt.extractSplits module

class hwtGraph.elk.fromHwt.extractSplits.InterfaceSplitInfo(iterable=(), /)

Bases: tuple

hwtGraph.elk.fromHwt.extractSplits.extractSplits(root: LNode)

convert group of indexed assignments witch are splitting signal to Split node

a = sig[0] b = sig[1] to a, b = sig

Parameters:

toL – dictionary {hdl object: layout object}

hwtGraph.elk.fromHwt.extractSplits.extractSplitsAsSingleNode(root: LNode, sliceParts: List[Tuple[slice, HdlAssignmentContainer, LNode]], toL: dict)

hwtGraph.elk.fromHwt.flattenTrees module

hwtGraph.elk.fromHwt.flattenTrees.collectNodesInTree(treeRoot: LNode, reducibleChildren: Set[LNode], reducedNodesSet: Set[LNode])

Collect nodes which will be reduced and input nodes of tree for tree of nodes.

Parameters:
  • treeRoot – root node of tree

  • reducibleChildren – members of tree

Returns:

Tuple[reducedNodes, inputEdges] where reducedNodes is List[LNode] and inputEdges is List[Tuple[LNode, LPort, LEdge]]

hwtGraph.elk.fromHwt.flattenTrees.flattenTrees(root, nodeSelector: Callable[[LNode], bool], reversePortOrder)

Walk all nodes and discover trees of nodes (usually operators) and reduce them to single node with multiple outputs

Attention:

selected nodes has to have single output and has to be connected to nets with single driver

hwtGraph.elk.fromHwt.flattenTrees.searchRootOfTree(reducibleChildren: Set[LNode], nodeFromTree: LNode, removedNodes: Set[LNode])

Walk tree of nodes to root

Parameters:
  • reducibleChildren – nodes which are part of tree

  • nodeFromTree – node where to start the search

hwtGraph.elk.fromHwt.mergeSplitsOnInterfaces module

class hwtGraph.elk.fromHwt.mergeSplitsOnInterfaces.MergeSplitsOnInterfacesCtx

Bases: object

iterPortSplits()
register(rootPort, splitOrConcat: LNode, mainEdge: LEdge)
class hwtGraph.elk.fromHwt.mergeSplitsOnInterfaces.PortConnectionCtx(iterable=(), /)

Bases: list

hwtGraph.elk.fromHwt.mergeSplitsOnInterfaces.copyPort(port, targetLNode, reverseDir, topPortName=None)

Create identical port on targetNode

hwtGraph.elk.fromHwt.mergeSplitsOnInterfaces.getRootIntfPort(port: LPort)
Returns:

most top port which contains this port

hwtGraph.elk.fromHwt.mergeSplitsOnInterfaces.mergeSplitsOnInterfaces(root: LNode)

collect all split/concatenation nodes and group them by target interface

hwtGraph.elk.fromHwt.mergeSplitsOnInterfaces.portCnt(port)

recursively count number of ports without children

hwtGraph.elk.fromHwt.mergeSplitsOnInterfaces.reconnectPorts(root: LNode, srcPort: LPort, oldSplits: List[Tuple[LNode, LEdge]], newSplitNode: LNode)
Variables:
  • ~.root – top LNode instance in which are nodes and links stored

  • ~.srcPort – for SLICE it is port which is connected to input of SLICE node for CONCAT it is port which is connected to output of CONCAT

  • ~.oldSplits – list of tuples (node, edge) which should be disconnected from graph

  • ~.newSplitNode – new node which should be connected to graph

hwtGraph.elk.fromHwt.mergeSplitsOnInterfaces.walkSignalPorts(rootPort: LPort)

recursively walk ports without any children

hwtGraph.elk.fromHwt.netCtx module

class hwtGraph.elk.fromHwt.netCtx.NetCtx(others: NetCtxs, actualKey, seqNo: int)

Bases: object

addDriver(src: RtlSignalBase | LPort)
addEndpoint(dst: RtlSignalBase | LPort)
extend(other: NetCtx)
class hwtGraph.elk.fromHwt.netCtx.NetCtxs(parentNode: LNode)

Bases: dict

Dictionary of NetCtx instances

applyConnections(root: LNode)
getDefault(k)
Returns:

tuple (value, True if key was there before else False)

joinNetsByKey(k0, k1)
joinNetsByKeyVal(k0, v1: NetCtx)
joinNetsByValKey(v0: NetCtx, k1)

hwtGraph.elk.fromHwt.netlistPreprocessors module

hwtGraph.elk.fromHwt.netlistPreprocessors.unhideResultsOfIndexingAndConcatOnPublicSignals(netlist: RtlNetlist)

hwtGraph.elk.fromHwt.propagatePresets module

class hwtGraph.elk.fromHwt.propagatePresets.HdlStatementCopier(stm: HdlStatement)

Bases: object

hwtGraph.elk.fromHwt.propagatePresets.propagatePresets(netlist: RtlNetlist)

Converts the format of statement branches into a format where each output is driven just by a single statement.

Note:

The example bellow is with a simple if and assignment but this function should convert any number of any statements.

c = 0
if b:
    c = 1

# to

if b:
    c = 1
else:
    c = 0
hwtGraph.elk.fromHwt.propagatePresets.propagatePresets_stm(stm: HdlStatement)
hwtGraph.elk.fromHwt.propagatePresets.propagatePresets_stm_list(stm_list: ListOfHdlStatement, output_sig: RtlSignal)

If multiple statements are driving output_sig merge them into just one.

hwtGraph.elk.fromHwt.reduceUselessAssignments module

hwtGraph.elk.fromHwt.reduceUselessAssignments.reduceUselessAssignments(root: LNode)

Remove assignments if it is only a direct connection and can be replaced with direct link

hwtGraph.elk.fromHwt.resolveSharedConnections module

hwtGraph.elk.fromHwt.resolveSharedConnections.countDirectlyConnected(port: LPort, result: dict) int

Count how many ports are directly connected to other nodes

Returns:

cumulative sum of port counts

hwtGraph.elk.fromHwt.resolveSharedConnections.getConnectedNode(port: LPort)
hwtGraph.elk.fromHwt.resolveSharedConnections.merge_non_reduced_ports(port: LPort, reduced_ports: List[LPort])
hwtGraph.elk.fromHwt.resolveSharedConnections.portTryReduce(root: LNode, port: LPort)

Check if majority of children is connected to same port if it is the case reduce children and connect this port instead children

Note:

use reduceUselessAssignments, extractSplits, flattenTrees before this function to maximize it’s effect

hwtGraph.elk.fromHwt.resolveSharedConnections.resolveSharedConnections(root: LNode)

Walk all ports on all nodes and group subinterface connections to only parent interface connection if it is possible

hwtGraph.elk.fromHwt.sortStatementPorts module

hwtGraph.elk.fromHwt.sortStatementPorts.sortStatementPorts(root: LNode)

hwtGraph.elk.fromHwt.statementRenderer module

class hwtGraph.elk.fromHwt.statementRenderer.StatementRenderer(node: LNode | VirtualLNode, toL, portCtx: Signal2stmPortCtx | None, rootNetCtxs: NetCtx)

Bases: object

Render nodes of statement into node or parent node

addInputPort(node, name, i: HValue | RtlSignalBase, side=PortSide.WEST)

Add and connect input port on subnode

Parameters:
  • node – node where to add input port

  • name – name of newly added port

  • i – input value

  • side – side where input port should be added

addOperatorAsLNode(op: Operator) LNode | NetCtx
addOutputPort(node: LNode, name: str, out: RtlSignalBase | LPort | None, origObj: RtlSignalBase | LPort, side=PortSide.EAST)

Add and connect output port on subnode

createAssignment(assig: HdlAssignmentContainer, connectOut: bool)
createFFNode(o: RtlSignalBase, clk: RtlSignalBase, i: RtlSignalBase, connectOut)
createMux(output: RtlSignalBase, inputs: List[RtlSignalBase | HValue], control: RtlSignalBase | List[RtlSignalBase], connectOut, latched=True)
createRamReadNode(mem: RtlSignalBase, clk: RtlSignalBase | None, addr: RtlSignalBase, out: RtlSignalBase, connectOut)
createRamWriteNode(mem: RtlSignalBase, clk: RtlSignalBase | None, addr: RtlSignalBase, inp: RtlSignalBase, w_en: RtlSignalBase | None, connectOut)
getInputNetCtx(signal: RtlSignalBase) NetCtx
lazyLoadNet(signal: RtlSignalBase)
Parameters:

signal – top signal of hidden operator tree

Note:

operator tree is constrained by signals with hidden==False

Note:

statement nodes are not connected automatically

renderContent()

Walk from outputs to inputs for each public signal register port of wrap node if required lazy load all operator and statement nodes for signals

renderEventDepIfContainer(ifStm: IfContainer, s: RtlSignalBase, connectOut)
renderForSignal(stm: HdlStatement | ListOfHdlStatement, s: RtlSignalBase, connectOut) Tuple[LNode, RtlSignalBase | LPort] | None

Walk statement and render nodes which are representing hardware components (MUX, LATCH, FF, …) for specified signal

hwtGraph.elk.fromHwt.statementRenderer.detectRamPorts(stm: IfContainer, current_en: RtlSignalBase)

Detect RAM ports in If statement

Parameters:
  • stm – statement to detect the ram ports in

  • current_en – current en/clk signal

hwtGraph.elk.fromHwt.statementRendererUtils module

class hwtGraph.elk.fromHwt.statementRendererUtils.Signal2stmPortCtx(stmNode: LNode)

Bases: object

getInside(sig: RtlSignalBase, portType: PortType)
getOutside(sig: RtlSignalBase, portType: PortType)
register(sig: RtlSignalBase, portType: PortType)
class hwtGraph.elk.fromHwt.statementRendererUtils.VirtualLNode(parent: LNode, stm: HdlStatement)

Bases: object

hwtGraph.elk.fromHwt.statementRendererUtils.addStmAsLNode(root: LNode, stm: HdlStatement, stmPorts: Dict[LNode, Signal2stmPortCtx], netCtx: NetCtxs) LNode
hwtGraph.elk.fromHwt.statementRendererUtils.walkStatementsForSig(statements: ListOfHdlStatement, s: RtlSignalBase)

hwtGraph.elk.fromHwt.utils module

hwtGraph.elk.fromHwt.utils.LNodeAddPortFromHdl(node, origin: Interface | HdlPortItem, direction: PortType, name: str)
hwtGraph.elk.fromHwt.utils.PortTypeFromDir(direction: INTF_DIRECTION)
hwtGraph.elk.fromHwt.utils.ValueAsLNode(root: LNode, val: HValue)
hwtGraph.elk.fromHwt.utils.addPort(n: LNode, intf: Interface)

Add LayoutExternalPort for interface and LPort instances to this LNode

hwtGraph.elk.fromHwt.utils.addPortToLNode(ln: LNode, intf: Interface, reverseDirection=False)
hwtGraph.elk.fromHwt.utils.getParentUnit(intf: Interface | Unit)
hwtGraph.elk.fromHwt.utils.getSinglePort(ports: List[LPort]) LEdge
hwtGraph.elk.fromHwt.utils.isUselessEq(op: Operator)
hwtGraph.elk.fromHwt.utils.isUselessTernary(op: Operator)
hwtGraph.elk.fromHwt.utils.originObjOfPort(intf: Interface)
hwtGraph.elk.fromHwt.utils.ternaryAsSimpleAssignment(root, op)
hwtGraph.elk.fromHwt.utils.toStr(obj)

Convert hwt object to string