hwtGraph.elk.fromHwt package¶

Submodules¶

hwtGraph.elk.fromHwt.convertor module¶

hwtGraph.elk.fromHwt.convertor.UnitToLNode(u: hwt.synthesizer.unit.Unit, node: Optional[hwtGraph.elk.containers.lNode.LNode] = None, toL: Optional[dict] = None, optimizations=[]) → hwtGraph.elk.containers.lNode.LNode ¶

Build LNode instance (a graph) from hwt.synthesizer.unit.Unit instance (a RTL graph)

Attention: unit has to be synthesized

hwtGraph.elk.fromHwt.defauts module¶

hwtGraph.elk.fromHwt.extractSplits module¶

class hwtGraph.elk.fromHwt.extractSplits.InterfaceSplitInfo(iterable=(), /)¶: Bases: tuple

hwtGraph.elk.fromHwt.extractSplits.extractSplits(root: hwtGraph.elk.containers.lNode.LNode)¶

convert group of indexed assignments witch are splitting signal to Split node

a = sig[0] b = sig[1] to a, b = sig

Parameters: toL – dictionary {hdl object: layout object}

hwtGraph.elk.fromHwt.extractSplits.extractSplitsAsSingleNode(root: hwtGraph.elk.containers.lNode.LNode, sliceParts: List[Tuple[slice, hwt.hdl.statements.assignmentContainer.HdlAssignmentContainer, hwtGraph.elk.containers.lNode.LNode]], toL: dict)¶

hwtGraph.elk.fromHwt.flattenTrees module¶

hwtGraph.elk.fromHwt.flattenTrees.collectNodesInTree(treeRoot: hwtGraph.elk.containers.lNode.LNode, reducibleChildren: Set[hwtGraph.elk.containers.lNode.LNode], reducedNodesSet: Set[hwtGraph.elk.containers.lNode.LNode])¶

Collect nodes which will be reduced and input nodes of tree for tree of nodes.

Parameters

treeRoot – root node of tree
reducibleChildren – members of tree

Returns

Tuple[reducedNodes, inputEdges] where reducedNodes is List[LNode] and inputEdges is List[Tuple[LNode, LPort, LEdge]]

hwtGraph.elk.fromHwt.flattenTrees.flattenTrees(root, nodeSelector: Callable[[hwtGraph.elk.containers.lNode.LNode], bool], reversePortOrder)¶

Walk all nodes and discover trees of nodes (usually operators) and reduce them to single node with multiple outputs

Attention: selected nodes has to have single output and has to be connected to nets with single driver

hwtGraph.elk.fromHwt.flattenTrees.searchRootOfTree(reducibleChildren: Set[hwtGraph.elk.containers.lNode.LNode], nodeFromTree: hwtGraph.elk.containers.lNode.LNode, removedNodes: Set[hwtGraph.elk.containers.lNode.LNode])¶

Walk tree of nodes to root

Parameters

reducibleChildren – nodes which are part of tree
nodeFromTree – node where to start the search

hwtGraph.elk.fromHwt.mergeSplitsOnInterfaces module¶

class hwtGraph.elk.fromHwt.mergeSplitsOnInterfaces.MergeSplitsOnInterfacesCtx¶

Bases: object

iterPortSplits()¶

register(rootPort, splitOrConcat: hwtGraph.elk.containers.lNode.LNode, mainEdge: hwtGraph.elk.containers.lEdge.LEdge)¶

class hwtGraph.elk.fromHwt.mergeSplitsOnInterfaces.PortConnectionCtx(iterable=(), /)¶: Bases: list

hwtGraph.elk.fromHwt.mergeSplitsOnInterfaces.copyPort(port, targetLNode, reverseDir, topPortName=None)¶: Create identical port on targetNode

hwtGraph.elk.fromHwt.mergeSplitsOnInterfaces.getRootIntfPort(port: hwtGraph.elk.containers.lPort.LPort)¶

Returns: most top port which contains this port

hwtGraph.elk.fromHwt.mergeSplitsOnInterfaces.mergeSplitsOnInterfaces(root: hwtGraph.elk.containers.lNode.LNode)¶: collect all split/concatenation nodes and group them by target interface

hwtGraph.elk.fromHwt.mergeSplitsOnInterfaces.portCnt(port)¶: recursively count number of ports without children

hwtGraph.elk.fromHwt.mergeSplitsOnInterfaces.reconnectPorts(root: hwtGraph.elk.containers.lNode.LNode, srcPort: hwtGraph.elk.containers.lPort.LPort, oldSplits: List[Tuple[hwtGraph.elk.containers.lNode.LNode, hwtGraph.elk.containers.lEdge.LEdge]], newSplitNode: hwtGraph.elk.containers.lNode.LNode)¶

Variables

root – top LNode instance in which are nodes and links stored
srcPort – for SLICE it is port which is connected to input of SLICE node for CONCAT it is port which is connected to output of CONCAT
oldSplits – list of tuples (node, edge) which should be disconnected from graph
newSplitNode – new node which should be connected to graph

hwtGraph.elk.fromHwt.mergeSplitsOnInterfaces.walkSignalPorts(rootPort: hwtGraph.elk.containers.lPort.LPort)¶: recursively walk ports without any children

hwtGraph.elk.fromHwt.netCtx module¶

class hwtGraph.elk.fromHwt.netCtx.NetCtx(others: hwtGraph.elk.fromHwt.netCtx.NetCtxs, actualKey, seqNo: int)¶

Bases: object

addDriver(src: Union[hwt.synthesizer.rtlLevel.mainBases.RtlSignalBase, hwtGraph.elk.containers.lPort.LPort])¶

addEndpoint(dst: Union[hwt.synthesizer.rtlLevel.mainBases.RtlSignalBase, hwtGraph.elk.containers.lPort.LPort])¶

extend(other: hwtGraph.elk.fromHwt.netCtx.NetCtx)¶

class hwtGraph.elk.fromHwt.netCtx.NetCtxs(parentNode: hwtGraph.elk.containers.lNode.LNode)¶

Bases: dict

Dictionary of NetCtx instances

applyConnections(root: hwtGraph.elk.containers.lNode.LNode)¶

getDefault(k)¶

Returns: tuple (value, True if key was there before else False)

joinNetsByKey(k0, k1)¶

joinNetsByKeyVal(k0, v1: hwtGraph.elk.fromHwt.netCtx.NetCtx)¶

joinNetsByValKey(v0: hwtGraph.elk.fromHwt.netCtx.NetCtx, k1)¶

hwtGraph.elk.fromHwt.netlistPreprocessors module¶

hwtGraph.elk.fromHwt.netlistPreprocessors.unhideResultsOfIndexingAndConcatOnPublicSignals(netlist: hwt.synthesizer.rtlLevel.netlist.RtlNetlist)¶

hwtGraph.elk.fromHwt.propagatePresets module¶

class hwtGraph.elk.fromHwt.propagatePresets.HdlStatementCopier(stm: hwt.hdl.statements.statement.HdlStatement)¶: Bases: object

hwtGraph.elk.fromHwt.propagatePresets.propagatePresets(netlist: hwt.synthesizer.rtlLevel.netlist.RtlNetlist)¶

Converts the format of statement branches into a format where each output is driven just by a single statement.

Note: The example bellow is with a simple if and assignment but this function should convert any number of any statements.

c = 0
if b:
    c = 1

# to

if b:
    c = 1
else:
    c = 0

hwtGraph.elk.fromHwt.propagatePresets.propagatePresets_stm(stm: hwt.hdl.statements.statement.HdlStatement)¶

hwtGraph.elk.fromHwt.propagatePresets.propagatePresets_stm_list(stm_list: List[hwt.hdl.statements.statement.HdlStatement], output_sig: hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal)¶: If multiple statements are driving output_sig merge them into just one.

hwtGraph.elk.fromHwt.reduceUselessAssignments module¶

hwtGraph.elk.fromHwt.reduceUselessAssignments.reduceUselessAssignments(root: hwtGraph.elk.containers.lNode.LNode)¶: Remove assignments if it is only a direct connection and can be replaced with direct link

hwtGraph.elk.fromHwt.resolveSharedConnections module¶

hwtGraph.elk.fromHwt.resolveSharedConnections.countDirectlyConnected(port: hwtGraph.elk.containers.lPort.LPort, result: dict) → int¶

Count how many ports are directly connected to other nodes

Returns: cumulative sum of port counts

hwtGraph.elk.fromHwt.resolveSharedConnections.getConnectedNode(port: hwtGraph.elk.containers.lPort.LPort)¶

hwtGraph.elk.fromHwt.resolveSharedConnections.merge_non_reduced_ports(port: hwtGraph.elk.containers.lPort.LPort, reduced_ports: List[hwtGraph.elk.containers.lPort.LPort])¶

hwtGraph.elk.fromHwt.resolveSharedConnections.portTryReduce(root: hwtGraph.elk.containers.lNode.LNode, port: hwtGraph.elk.containers.lPort.LPort)¶

Check if majority of children is connected to same port if it is the case reduce children and connect this port instead children

Note: use reduceUselessAssignments, extractSplits, flattenTrees before this function to maximize it’s effect

hwtGraph.elk.fromHwt.resolveSharedConnections.resolveSharedConnections(root: hwtGraph.elk.containers.lNode.LNode)¶: Walk all ports on all nodes and group subinterface connections to only parent interface connection if it is possible

hwtGraph.elk.fromHwt.sortStatementPorts module¶

hwtGraph.elk.fromHwt.sortStatementPorts.sortStatementPorts(root: hwtGraph.elk.containers.lNode.LNode)¶

hwtGraph.elk.fromHwt.statementRenderer module¶

class hwtGraph.elk.fromHwt.statementRenderer.StatementRenderer(node: Union[hwtGraph.elk.containers.lNode.LNode, hwtGraph.elk.fromHwt.statementRendererUtils.VirtualLNode], toL, portCtx: Optional[hwtGraph.elk.fromHwt.statementRendererUtils.Signal2stmPortCtx], rootNetCtxs: hwtGraph.elk.fromHwt.netCtx.NetCtx)¶

Bases: object

Render nodes of statement into node or parent node

addInputPort(node, name, i: Union[hwt.hdl.value.HValue, hwt.synthesizer.rtlLevel.mainBases.RtlSignalBase], side=<PortSide.WEST: 1>)¶

Add and connect input port on subnode

Parameters

node – node where to add input port
name – name of newly added port
i – input value
side – side where input port should be added

addOperatorAsLNode(op: hwt.hdl.operator.Operator) → Union[hwtGraph.elk.containers.lNode.LNode, hwtGraph.elk.fromHwt.netCtx.NetCtx]¶

addOutputPort(node: hwtGraph.elk.containers.lNode.LNode, name: str, out: Optional[Union[hwt.synthesizer.rtlLevel.mainBases.RtlSignalBase, hwtGraph.elk.containers.lPort.LPort]], origObj: Union[hwt.synthesizer.rtlLevel.mainBases.RtlSignalBase, hwtGraph.elk.containers.lPort.LPort], side=<PortSide.EAST: 0>)¶: Add and connect output port on subnode

createAssignment(assig: hwt.hdl.statements.assignmentContainer.HdlAssignmentContainer, connectOut: bool)¶

createFFNode(o: hwt.synthesizer.rtlLevel.mainBases.RtlSignalBase, clk: hwt.synthesizer.rtlLevel.mainBases.RtlSignalBase, i: hwt.synthesizer.rtlLevel.mainBases.RtlSignalBase, connectOut)¶

createMux(output: hwt.synthesizer.rtlLevel.mainBases.RtlSignalBase, inputs: List[Union[hwt.synthesizer.rtlLevel.mainBases.RtlSignalBase, hwt.hdl.value.HValue]], control: Union[hwt.synthesizer.rtlLevel.mainBases.RtlSignalBase, List[hwt.synthesizer.rtlLevel.mainBases.RtlSignalBase]], connectOut, latched=True)¶

createRamReadNode(mem: hwt.synthesizer.rtlLevel.mainBases.RtlSignalBase, clk: Optional[hwt.synthesizer.rtlLevel.mainBases.RtlSignalBase], addr: hwt.synthesizer.rtlLevel.mainBases.RtlSignalBase, out: hwt.synthesizer.rtlLevel.mainBases.RtlSignalBase, connectOut)¶

createRamWriteNode(mem: hwt.synthesizer.rtlLevel.mainBases.RtlSignalBase, clk: Optional[hwt.synthesizer.rtlLevel.mainBases.RtlSignalBase], addr: hwt.synthesizer.rtlLevel.mainBases.RtlSignalBase, inp: hwt.synthesizer.rtlLevel.mainBases.RtlSignalBase, w_en: Optional[hwt.synthesizer.rtlLevel.mainBases.RtlSignalBase], connectOut)¶

getInputNetCtx(signal: hwt.synthesizer.rtlLevel.mainBases.RtlSignalBase) → hwtGraph.elk.fromHwt.netCtx.NetCtx ¶

lazyLoadNet(signal: hwt.synthesizer.rtlLevel.mainBases.RtlSignalBase)¶

Parameters: signal – top signal of hidden operator tree
Note: operator tree is constrained by signals with hidden==False
Note: statement nodes are not connected automatically

renderContent()¶: Walk from outputs to inputs for each public signal register port of wrap node if required lazy load all operator and statement nodes for signals

renderEventDepIfContainer(ifStm: hwt.hdl.statements.ifContainter.IfContainer, s: hwt.synthesizer.rtlLevel.mainBases.RtlSignalBase, connectOut)¶

renderForSignal(stm: Union[hwt.hdl.statements.statement.HdlStatement, List[hwt.hdl.statements.statement.HdlStatement]], s: hwt.synthesizer.rtlLevel.mainBases.RtlSignalBase, connectOut) → Optional[Tuple[hwtGraph.elk.containers.lNode.LNode, Union[hwt.synthesizer.rtlLevel.mainBases.RtlSignalBase, hwtGraph.elk.containers.lPort.LPort]]]¶: Walk statement and render nodes which are representing hardware components (MUX, LATCH, FF, …) for specified signal

hwtGraph.elk.fromHwt.statementRenderer.detectRamPorts(stm: hwt.hdl.statements.ifContainter.IfContainer, current_en: hwt.synthesizer.rtlLevel.mainBases.RtlSignalBase)¶

Detect RAM ports in If statement

Parameters

stm – statement to detect the ram ports in
current_en – current en/clk signal

hwtGraph.elk.fromHwt.statementRendererUtils module¶

class hwtGraph.elk.fromHwt.statementRendererUtils.Signal2stmPortCtx(stmNode: hwtGraph.elk.containers.lNode.LNode)¶

Bases: object

getInside(sig: hwt.synthesizer.rtlLevel.mainBases.RtlSignalBase, portType: hwtGraph.elk.containers.constants.PortType)¶

getOutside(sig: hwt.synthesizer.rtlLevel.mainBases.RtlSignalBase, portType: hwtGraph.elk.containers.constants.PortType)¶

register(sig: hwt.synthesizer.rtlLevel.mainBases.RtlSignalBase, portType: hwtGraph.elk.containers.constants.PortType)¶

class hwtGraph.elk.fromHwt.statementRendererUtils.VirtualLNode(parent: hwtGraph.elk.containers.lNode.LNode, stm: hwt.hdl.statements.statement.HdlStatement)¶: Bases: object

hwtGraph.elk.fromHwt.statementRendererUtils.addStmAsLNode(root: hwtGraph.elk.containers.lNode.LNode, stm: hwt.hdl.statements.statement.HdlStatement, stmPorts: Dict[hwtGraph.elk.containers.lNode.LNode, hwtGraph.elk.fromHwt.statementRendererUtils.Signal2stmPortCtx], netCtx: hwtGraph.elk.fromHwt.netCtx.NetCtxs) → hwtGraph.elk.containers.lNode.LNode ¶

hwtGraph.elk.fromHwt.statementRendererUtils.walkStatementsForSig(statements: List[hwt.hdl.statements.statement.HdlStatement], s: hwt.synthesizer.rtlLevel.mainBases.RtlSignalBase)¶

hwtGraph.elk.fromHwt.utils module¶

hwtGraph.elk.fromHwt.utils.LNodeAddPortFromHdl(node, origin: Union[hwt.synthesizer.interface.Interface, hwt.hdl.portItem.HdlPortItem], direction: hwtGraph.elk.containers.constants.PortType, name: str)¶

hwtGraph.elk.fromHwt.utils.PortTypeFromDir(direction: ipCorePackager.constants.INTF_DIRECTION)¶

hwtGraph.elk.fromHwt.utils.ValueAsLNode(root: hwtGraph.elk.containers.lNode.LNode, val: hwt.hdl.value.HValue)¶

hwtGraph.elk.fromHwt.utils.addPort(n: hwtGraph.elk.containers.lNode.LNode, intf: hwt.synthesizer.interface.Interface)¶: Add LayoutExternalPort for interface and LPort instances to this LNode

hwtGraph.elk.fromHwt.utils.addPortToLNode(ln: hwtGraph.elk.containers.lNode.LNode, intf: hwt.synthesizer.interface.Interface, reverseDirection=False)¶

hwtGraph.elk.fromHwt.utils.getParentUnit(intf: Union[hwt.synthesizer.interface.Interface, hwt.synthesizer.unit.Unit])¶

hwtGraph.elk.fromHwt.utils.getSinglePort(ports: List[hwtGraph.elk.containers.lPort.LPort]) → hwtGraph.elk.containers.lEdge.LEdge ¶

hwtGraph.elk.fromHwt.utils.isUselessEq(op: hwt.hdl.operator.Operator)¶

hwtGraph.elk.fromHwt.utils.isUselessTernary(op: hwt.hdl.operator.Operator)¶

hwtGraph.elk.fromHwt.utils.originObjOfPort(intf: hwt.synthesizer.interface.Interface)¶

hwtGraph.elk.fromHwt.utils.ternaryAsSimpleAssignment(root, op)¶

hwtGraph.elk.fromHwt.utils.toStr(obj)¶: Convert hwt object to string